//am29200.h
//memory mapped registers for the AMD AM29200 processor
//displacements relative to 0x80000000
//to be used as index in array
//19930609/wjvg

#define DMEM_RMCT  0x00  //ROM control register
#define DMEM_RMCF  0x04  //ROM configuration register
#define DMEM_DRCT  0x08  //DRAM control register
#define DMEM_DRCF  0x0c  //DRAM configuration register

#define DMEM_DRM0  0x10  //DRAM mapping register 0
#define DMEM_DRM1  0x14  //DRAM mapping register 1
#define DMEM_DRM2  0x18  //DRAM mapping register 2
#define DMEM_DRM3  0x1c  //DRAM mapping register 3

#define DMEM_PICT0 0x20  //PIA control register 0
#define DMEM_PICT1 0x24  //PIA control register 1
#define DMEM_ICT   0x28  //interrupt control register

#define DMEM_DMCT0 0x30  //DMA0 control register
#define DMEM_DMAD0 0x34  //DMA0 address register
#define DMEM_TAD0  0x36  //DMA0 address tail register
#define DMEM_DMCN0 0x38  //DMA0 count register
#define DMEM_TCN0  0x3a  //DMA0 count tail register

#define DMEM_DMCT1 0x40  //DMA1 control register
#define DMEM_DMAD1 0x44  //DMA1 address register
#define DMEM_TAD1  0x46  //DMA1 address tail register
#define DMEM_DMCN1 0x48  //DMA1 count register
#define DMEM_TCN1  0x4a  //DMA1 count tail register

#define DMEM_SPCT  0x80  //serial port control register
#define DMEM_SPST  0x84  //serial port status register
#define DMEM_SPTH  0x88  //serial port transmit holding register
#define DMEM_SPRB  0x8c  //serial port receive buffer register

#define DMEM_BAUD  0x90  //baud rate divisor register
#define DMEM_PPCT  0xc0  //parallel port control register
#define DMEM_PPST  0xc1  //parallel port status register
#define DMEM_PPDT  0xc4  //parallel port data register

#define DMEM_POCT  0xd0  //PIO control register
#define DMEM_PIN   0xd4  //PIO input register
#define DMEM_POUT  0xd8  //PIO output register
#define DMEM_POEN  0xdc  //PIO output enable register

#define DMEM_VCT   0xe0  //video control register
#define DMEM_TOP   0xe4  //video margin register
#define DMEM_SIDE  0xe8  //side margin register
#define DMEM_VDT   0xec  //video data holding register

//end