//am7990.h
//Local area controller for ethernet (LANCE)
//19940122/wjvg

//the ports:
#define RDP 0  //register data port
#define RAP 1  //register address port

//registers to be chooesen in RAP:
#define RAP_CSR0 0  //control and status register 0
#define RAP_CSR1 1  //control and status register 1
#define RAP_CSR2 2  //control and status register 2
#define RAP_CSR3 3  //control and status register 3

//initialization block
struct am7990_init {
  unsigned short mode;
  unsigned char  Apaddr[6];   //physical (net)address, bits  0.<48
  unsigned long  Aladdrf[2];  //logical (net)addressfilter, bits  0.<32 en 32.<64
  unsigned long  rdra;        //rec descr ring pointer, bits 0.<24, rx length
  unsigned long  tdra;        //tra descr ring pointer, bits 0.<24, tx length
};

//receive descriptor
struct am7990_rd {
  unsigned long  base;       //base of buffer
  unsigned short neglength;  //negative length of buffer
  unsigned short reclength;  //length of message
};

//transmit descriptor
struct am7990_td {
  unsigned long  base;       //base of buffer
  unsigned short neglength;  //negative length of buffer
  unsigned short misc;       //miscellaneous
};

//control and status register 0
#define CSR0_INIT (1<< 0)  //init
#define CSR0_STRT (1<< 1)  //start
#define CSR0_STOP (1<< 2)  //stop
#define CSR0_TDMD (1<< 3)  //transmit demand
#define CSR0_TXON (1<< 4)  //transmitter on
#define CSR0_RXON (1<< 5)  //receiver on
#define CSR0_INEA (1<< 6)  //interrupt enable
#define CSR0_INTR (1<< 7)  //interrupt flag
#define CSR0_IDON (1<< 8)  //initialization done
#define CSR0_TINT (1<< 9)  //transmitter interrupt
#define CSR0_RINT (1<<10)  //receiver interrupt
#define CSR0_MERR (1<<11)  //memory error
#define CSR0_MISS (1<<12)  //missed packet
#define CSR0_CERR (1<<13)  //collision error
#define CSR0_BABL (1<<14)  //babble, transmitter timeout error
#define CSR0_ERR  (1<<15)  //error summary

//control and status register 3
#define CSR3_BCON (1<< 0)  //byte control: p16=busako/bm,
                           //p15=byte/bm0, p17=busrq/hold
#define CSR3_ACON (1<< 1)  //ALE control: ALE asserted H/L
#define CSR3_BSWP (1<< 2)  //byte swap: big/little endian, big=68000 etc.

//initialization mode
#define MODE_DRX  (1<< 0)  //disable the receiver
#define MODE_DTX  (1<< 1)  //disable the transmitter
#define MODE_LOOP (1<< 2)  //loopback, for test purposes
#define MODE_DTCR (1<< 3)  //disable transmit CRC
#define MODE_COLL (1<< 4)  //force collision
#define MODE_DRTY (1<< 5)  //disable retry
#define MODE_INTL (1<< 6)  //internal loopback
#define MODE_PROM (1<<15)  //promiscuous mode: accept all incoming packets

//receive descriptor ring address
#define RDRA_RLEN (1<<29)  //receive ring length, (log2 of)

//transmit descriptor ring address
#define TDRA_TLEN (1<<29)  //transmit ring length, (log2 of)

//receive message descriptor 1
#define RMD1_ENP  (1<< 8+16)  //end of packet
#define RMD1_STP  (1<< 9+16)  //start of packet
#define RMD1_BUFF (1<<10+16)  //buffer error
#define RMD1_CRC  (1<<11+16)  //CRC-error
#define RMD1_OFLO (1<<12+16)  //overflow error
#define RMD1_FRAM (1<<13+16)  //framing error
#define RMD1_ERR  (1<<14+16)  //error summary, is FRAM|OFLO|CRC|BUFF
#define RMD1_OWN  (1<<15+16)  //owned by am7990/cpu

//transmit message descriptor 1
#define TMD1_ENP  (1<< 8+16)  //end of packet
#define TMD1_STP  (1<< 9+16)  //start of packet
#define TMD1_DEF  (1<<10+16)  //buffer error
#define TMD1_ONE  (1<<11+16)  //CRC-error
#define TMD1_MORE (1<<12+16)  //overflow error
#define TMD1_RES  (1<<13+16)  //framing error
#define TMD1_ERR  (1<<14+16)  //error summary, is FRAM|OFLO|CRC|BUFF
#define TMD1_OWN  (1<<15+16)  //owned by am7990/cpu

//transmit message descriptor 3
#define TMD3_TDR  (1<< 0)  //time domain reflectometry
#define TMD3_RTRY (1<<10)  //retry error
#define TMD3_LCAR (1<<11)  //loss of carrier
#define TMD3_LCOL (1<<12)  //late collision
#define TMD3_RES  (1<<13)  //reserved
#define TMD3_UFLO (1<<14)  //underflow error
#define TMD3_BUFF (1<<15)  //buffer error

//end