//m6811f.h //registerfields in the 6811 //19940718/wjvg, copied from .. //******************************************************************** //Address Name Function //------- ---- ---------------------------------------- //0x00 PORTA I/O Port A (3 In only, 5 Out only) //0x01 Reserved //0x02 PIOC Parallel I/O Control Register //0x03 PORTC I/O Port C //0x04 PORTB I/O Port B (Output only) //0x05 PORTCL Alternate Latched Port C //0x07 DDRC Data Direction for Port C //0x08 PORTD I/O Port D //0x09 DDRD Data Direction for Port D //0x0a PORTE I/O Port E (Input only) //0x0b CFORC Compare Force Register //0x0c OC1M OC1 Action Mask Register //0x0d OC1D OC1 Action Data Register //0x0e,0f TCNT Timer Counter Register //0x10,11 TIC1 Input Capture 1 Register //0x12,13 TIC2 Input Capture 2 Register //0x14,15 TIC3 Input Capture 3 Register //0x16,17 TOC1 Output Compare 1 Register //0x18,19 TOC2 Output Compare 2 Register //0x1a,1b TOC3 Output Compare 3 Register //0x1c,1d TOC4 Output Compare 4 Register //0x1e,1f TOC5 Output Compare 5 Register //0x20 TCTL1 Timer Control Register 1 //0x21 TCTL2 Timer Control Register 2 //0x22 TMSK1 Main Timer Interrupt Mask Register 1 //0x23 TFLG1 Main Timer Interrupt Flag Register 1 //0x24 TMSK2 Main Timer Interrupt Mask Register 2 //0x25 TFLG2 Main Timer Interrupt Flag Register 2 //0x26 PACTL Pulse Accumulator Control Register //0x27 PACNT Pulse Accumulator Count Register //0x28 SPCR SPI Control Register //0x29 SPSR SPI Status Register //0x2a SPDAT SPI Date In/Out //0x2b BAUD SPI Baud Rate Control //0x2c SCCR1 SCI Control Register 1 //0x2d SCCR2 SCI Control Register 2 //0x2e SCSR SCI Status Register //0x2f SCDAT SCI Data (Read RDR, Write TDR) //0x30 ADCTL A to D Control Register //0x31 ADR1 A to D Result Register 1 //0x32 ADR2 A to D Result Register 2 //0x33 ADR3 A to D Result Register 3 //0x34 ADR4 A to D Result Register 4 //0x35 BPROT EEPROM Block Protect Register //0x36 Reserved //0x37 Reserved //0x38 Reserved //0x39 OPTION System Configuration Options //0x3a COPRST Arm/Reset COP Timer Circuitry //0x3b PROG EEPROM Programming Control Register //0x3c HPRIO Highest Priority I-bit Interrupt and Misc //0x3d INIT RAM - I/O Mapping Register //0x3e TEST1 Factory TEST Control Register //0x3f CONFIG COP, ROM & EEPROM enables (EEPROM cells) //PORTA 0x00 Port A Data Register #define PA7 0x80 //Port A Data bit 7 #define PA6 0x40 //Port A Data bit 6 #define PA5 0x20 //Port A Data bit 5 #define PA4 0x10 //Port A Data bit 4 #define PA3 0x08 //Port A Data bit 3 #define PA2 0x04 //Port A Data bit 2 #define PA1 0x02 //Port A Data bit 1 #define PA0 0x01 //Port A Data bit 0 //PIOC 0x02 Parallel I/O Control Register #define STAF 0x80 //Strobe A Input Status Flag #define STAI 0x40 //Strobe A Interrupt Enable Mask #define CWOM 0x20 //Port C Wire-Or Mode #define HNDS 0x10 //Handshake Modes #define OIN 0x08 //Output or Input Handshaking #define PLS 0x04 //Pulse/Interlocked Handshake Operation #define EGA 0x02 //Active Edge for STRA #define INVB 0x01 //Invert Strobe B //PORTC 0x03 Port C Data Register #define PC7 0x80 //Port C Data bit 7 #define PC6 0x40 //Port C Data bit 6 #define PC5 0x20 //Port C Data bit 5 #define PC4 0x10 //Port C Data bit 4 #define PC3 0x08 //Port C Data bit 3 #define PC2 0x04 //Port C Data bit 2 #define PC1 0x02 //Port C Data bit 1 #define PC0 0x01 //Port C Data bit 0 //PORTB 0x04 Port B Data Register (Output only) #define PB7 0x80 //Port B Data bit 7 #define PB6 0x40 //Port B Data bit 6 #define PB5 0x20 //Port B Data bit 5 #define PB4 0x10 //Port B Data bit 4 #define PB3 0x08 //Port B Data bit 3 #define PB2 0x04 //Port B Data bit 2 #define PB1 0x02 //Port B Data bit 1 #define PB0 0x01 //Port B Data bit 0 //PORTCL 0x05 Alternate Latched Port C #define PCL7 0x80 //Port C Latched Data bit 7 #define PCL6 0x40 //Port C Latched Data bit 6 #define PCL5 0x20 //Port C Latched Data bit 5 #define PCL4 0x10 //Port C Latched Data bit 4 #define PCL3 0x08 //Port C Latched Data bit 3 #define PCL2 0x04 //Port C Latched Data bit 2 #define PCL1 0x02 //Port C Latched Data bit 1 #define PCL0 0x01 //Port C Latched Data bit 0 //DDRC 0x07 Data Direction for Port C #define DDC7 0x80 //Data Direction for Port C bit 7 #define DDC6 0x40 //Data Direction for Port C bit 6 #define DDC5 0x20 //Data Direction for Port C bit 5 #define DDC4 0x10 //Data Direction for Port C bit 4 #define DDC3 0x08 //Data Direction for Port C bit 3 #define DDC2 0x04 //Data Direction for Port C bit 2 #define DDC1 0x02 //Data Direction for Port C bit 1 #define DDC0 0x01 //Data Direction for Port C bit 0 //PORTD 0x08 Port D Data Register #define PD5 0x20 //Port D Data bit 5 #define PD4 0x10 //Port D Data bit 4 #define PD3 0x08 //Port D Data bit 3 #define PD2 0x04 //Port D Data bit 2 #define PD1 0x02 //Port D Data bit 1 #define PD0 0x01 //Port D Data bit 0 //DDRD 0x09 Data Direction for Port D #define DDRD5 0x20 //Data Direction register for Port D bit 5 #define DDRD4 0x10 //Data Direction register for Port D bit 4 #define DDRD3 0x08 //Data Direction register for Port D bit 3 #define DDRD2 0x04 //Data Direction register for Port D bit 2 #define DDRD1 0x02 //Data Direction register for Port D bit 1 #define DDRD0 0x01 //Data Direction register for Port D bit 0 #define SS DDRD5 //serial select #define SCK DDRD4 //serial select #define MOSI DDRD3 //serial select #define MISO DDRD2 //serial select #define TXD DDRD1 //serial select #define RXD DDRD0 //serial select //PORTE 0x0a Port E Data Register (Input only) #define PE7 0x80 //Port E Data bit 7 #define PE6 0x40 //Port E Data bit 6 #define PE5 0x20 //Port E Data bit 5 #define PE4 0x10 //Port E Data bit 4 #define PE3 0x08 //Port E Data bit 3 #define PE2 0x04 //Port E Data bit 2 #define PE1 0x02 //Port E Data bit 1 #define PE0 0x01 //Port E Data bit 0 //CFORC 0x0b Compare Force Register #define FOC1 0x80 //Force Output Compare 1 Action #define FOC2 0x40 //Force Output Compare 2 Action #define FOC3 0x20 //Force Output Compare 3 Action #define FOC4 0x10 //Force Output Compare 4 Action #define FOC5 0x08 //Force Output Compare 5 Action //OC1M 0x0c OC1 Action Mask Register #define OC1M7 0x80 //Output Compare 1 Mask bit 7 #define OC1M6 0x40 //Output Compare 2 Mask bit 6 #define OC1M5 0x20 //Output Compare 3 Mask bit 5 #define OC1M4 0x10 //Output Compare 4 Mask bit 4 #define OC1M3 0x08 //Output Compare 5 Mask bit 3 //OC1D 0x0d OC1 Action Data Register #define OC1D7 0x80 //Output Compare 1 Data bit 7 #define OC1D6 0x40 //Output Compare 2 Data bit 6 #define OC1D5 0x20 //Output Compare 3 Data bit 5 #define OC1D4 0x10 //Output Compare 4 Data bit 4 #define OC1D3 0x08 //Output Compare 5 Data bit 3 //TCNT 0x0e Timer Counter Register #define TIC1 0x10 //Input Capture 1 Register #define TIC2 0x12 //Input Capture 2 Register #define TIC3 0x14 //Input Capture 3 Register #define TOC1 0x16 //Output Compare 1 Register #define TOC2 0x18 //Output Compare 2 Register #define TOC3 0x1a //Output Compare 3 Register #define TOC4 0x1c //Output Compare 4 Register #define TOC5 0x1e //Output Compare 5 Register #define TIC4 TOC5 //Input Capture 4 Register //TCTL1 0x20 Timer Control Register 1 #define OM2 0x80 //Output Mode #define OL2 0x40 //Output Level #define OM3 0x20 //Output Mode #define OL3 0x10 //Output Level #define OM4 0x08 //Output Mode #define OL4 0x04 //Output Level #define OM5 0x02 //Output Mode #define OL5 0x01 //Output Level //TCTL2 0x21 Timer Control Register 2 #define EDG4B 0x80 //Input Capture edge control 4B #define EDG4A 0x40 //Input Capture edge control 4A #define EDG1B 0x20 //Input Capture edge control 1B #define EDG1A 0x10 //Input Capture edge control 1A #define EDG2B 0x08 //Input Capture edge control 2B #define EDG2A 0x04 //Input Capture edge control 2A #define EDG3B 0x02 //Input Capture edge control 3B #define EDG3A 0x01 //Input Capture edge control 3A //TMSK1 0x22 Main Timer Interrupt Mask Register 1 #define OC1I 0x80 //Output Compare 1 Interrupt Enable #define OC2I 0x40 //Output Compare 2 Interrupt Enable #define OC3I 0x20 //Output Compare 3 Interrupt Enable #define OC4I 0x10 //Output Compare 4 Interrupt Enable #define OC5I 0x08 //Output Compare 5 Interrupt Enable #define IC1I 0x04 //Input Compare 1 Interrupt Enable #define IC2I 0x02 //Input Compare 2 Interrupt Enable #define IC3I 0x01 //Input Compare 3 Interrupt Enable #define IC4I OC5I //Input Compare 4 Interrupt Enable //TFLG1 0x23 Main Timer Interrupt Flag Register 1 #define OC1F 0x80 //Output Compare 1 Flag #define OC2F 0x40 //Output Compare 2 Flag #define OC3F 0x20 //Output Compare 3 Flag #define OC4F 0x10 //Output Compare 4 Flag #define OC5F 0x08 //Output Compare 5 Flag #define IC1F 0x04 //Input Compare 1 Flag #define IC2F 0x02 //Input Compare 2 Flag #define IC3F 0x01 //Input Compare 3 Flag #define IC4F OC5F //Input Compare 4 Flag //TMSK2 0x24 Misc Timer Interrupt Mask Register 2 #define TOI 0x80 //Timer Overflow Interrupt enable #define RTII 0x40 //RTI Interrupt enable #define PAOVI 0x20 //Pulse Accumulator Overflow Interrupt #define PAII 0x10 //Pulse Accumulator Input Interrupt enable #define PR1 0x02 //Timer Prescaller select 1 #define PR2 0x01 //Timer Prescaller select 2 //TFLG2 0x25 Misc Timer Interrupt Flag Register 2 #define TOF 0x80 //Timer Overflow Flag #define RTIF 0x40 //Real Time (periodic) Interrupt Flag #define PAOVF 0x20 //Pulse Accumulator Overflow Flag #define PAIF 0x10 //Pulse Accumulator Input edge Flag //PACTL 0x26 Pulse Accumulator Control Register #define DDRA7 0x80 //Data Direction for Port A bit 7 #define PAEN 0x40 //Pulse Accumulator system ENable #define PAMOD 0x20 //Pulse Accumulator MODe #define PEDGE 0x10 //Pulse Accumulator Edge Control #define DDRA3 0x08 //Data Direction for Port A bit 3 #define I4_O5 0x04 //Input Capture 4 (=1)/Output Compare 5 (=0) #define RTR1 0x02 //RTI Interrupt Rate 1 #define RTR0 0x01 //RTI Interrupt Rate 0 //PACNT 0x27 Pulse Accumulator Count Register //SPCR 0x28 SPI Control Register #define SPIE 0x80 //SPI Control Register #define SPE 0x40 //SPI Interrupt Enable #define DWOM 0x20 //Port D Wire-Or Mode #define MSTR 0x10 //Master Mode Select #define CPOL 0x08 //Clock Polarity #define CPHA 0x04 //Clock Phase #define SPR1 0x02 //SPI Rate Select bit 1 #define SPR0 0x01 //SPI Rate Select bit 0 //SPSR 0x29 SPI Status Register #define SPIF 0x80 //SPI Interrupt Status Flag #define WCOL 0x40 //SPI Write Collision Status Falg #define MODF 0x10 //SPI Mode Fault Interrupt Status Flag //SPDAT 0x2a SPI Date In/Out //BAUD 0x2b SPI Baud Rate Control #define TCLR 0x80 //Test/Clear Baud Rate Counters #define SCP1 0x20 //Serial Prescaler Selects 1 #define SCP0 0x10 //Serial Prescaler Selects 0 #define RCKB 0x08 //SCI Receiver Test Bit #define SCR2 0x04 //SCI Rate Select bit 2 #define SCR1 0x02 //SCI Rate Select bit 1 #define SCR0 0x01 //SCI Rate Select bit 0 //SCCR1 0x2c SCI Control Register 1 #define R8 0x80 //Receive bit 8 #define T8 0x40 //Transmit bit 8 #define M 0x10 //SCI Mode Select #define WAKE 0x08 //Wake Up by Address Mark / Idle //SCCR2 0x2d SCI Control Register 2 #define TIE 0x80 //Transmit Interrupt Enable #define TCIE 0x40 //Transmit Complete Interrupt Enable #define RIE 0x20 //Receiver Interrupt Enable #define ILIE 0x10 //Idle Line Interrupt Enable #define TE 0x08 //Transmitter Enable #define RE 0x04 //Receiver Enable #define RWU 0x02 //Receiver Wake-up Control #define SBK 0x01 //Send Break //SCSR 0x2e SCI Status Register #define TDRE 0x80 //Transmit Data Register Empty Flag #define TC 0x40 //Transmit Complete Flag #define RDRF 0x20 //Receive Data Register Full Flag #define IDLE 0x10 //Idle Line Detected Flag #define OR 0x08 //Over-run flag #define NF 0x04 //Noise Error Flag #define FE 0x02 //Framing Error Flag //SCDAT 0x2f SCI Data (Read RDR, Write TDR) //ADCTL 0x30 A to D Control Register #define CCF 0x80 //Conversion Complete Flag #define SCAN 0x20 //Continuous Scan Control #define MULT 0x10 //Multiple Channel / Single Channel control #define CD 0x08 //Channel Select D #define CC 0x04 //Channel Select C #define CB 0x02 //Channel Select B #define CA 0x01 //Channel Select A //ADR1 0x31 A to D Result Register 1 //ADR2 0x32 A to D Result Register 2 //ADR3 0x33 A to D Result Register 3 //ADR4 0x34 A to D Result Register 4 //BPROT 0x35 EEPROM Block Protect Register #define PTCON 0x10 //Protect CONFIG Register // . =1 disables programming/erasure, =0 enables #define BPRT3 0x08 //Block Protect $B600-B61F ( 32 bytes) #define BPRT2 0x04 //Block Protect $B620-B65F ( 64 bytes) #define BPRT1 0x02 //Block Protect $B660-B6DF (128 bytes) #define BPRT0 0x01 //Block Protect $B6E0-B7FF (288 bytes) //OPTION 0x39 System Configuration Options #define ADPU 0x80 //A to D Power Up #define CSEL 0x40 //A to D Clock Select #define IRQE 0x20 //IRQ Select Edge Sensitive Only #define DLY 0x10 //Enable Oscillator Start-up delay #define CME 0x08 //Clock Monitor Enable #define CR1 0x02 //COP Timer Rate Select bit 1 #define CR0 0x01 //COP Timer Rate Select bit 0 //COPRST 0x3a Arm/Reset COP Timer Circuitry //PPROG 0x3b EEPROM Programming Control Register #define ODD 0x80 //Program Odd Rows in Test #define EVEN 0x40 //Program Even Rows in Test #define ASEL 0x20 //Array Select #define BYTE 0x10 //Select Byte Erase Mode for the EEPROM #define ROW 0x08 //Row/All EEPROM Erase Mode #define ERASE 0x04 //Erase/Normal Control for EEPROM #define EELAT 0x02 //EEPROM Latch Control #define EEPGM 0x01 //EEPROM Program Command //HPRIO 0x3c Highest Priority I-bit Interrupt and Misc #define RBOOT 0x80 //Read Bootstrap ROM #define SMOD 0x40 //Special Mode #define MDA 0x20 //Mode Select A #define IRV 0x10 //Internal Read Visibility #define PSEL3 0x08 //Priority Select bit 3 #define PSEL2 0x04 //Priority Select bit 2 #define PSEL1 0x02 //Priority Select bit 1 #define PSEL0 0x01 //Priority Select bit 0 //INIT 0x3d RAM - I/O Mapping Register #define RAM3 0x80 //RAM Map Position bit 3 #define RAM2 0x40 //RAM Map Position bit 2 #define RAM1 0x20 //RAM Map Position bit 1 #define RAM0 0x10 //RAM Map Position bit 0 #define REG3 0x08 //64-byte Register block Map Position bit 3 #define REG2 0x04 //64-byte Register block Map Position bit 2 #define REG1 0x02 //64-byte Register block Map Position bit 1 #define REG0 0x01 //64-byte Register block Map Position bit 0 //TEST1 0x3e Factory TEST Control Register #define TILOP 0x80 //Test Illegal Opcode #define OCCR 0x20 //Output Condition Code Register to Timer #define CBYP 0x10 //Timer Divider Chain Bypass #define DISR 0x08 //Disable Resets from COP and Clock Monitor #define FCM 0x04 //Force Clock Monitor Failure #define FCOP 0x02 //Force COP Watchdog Failure #define TCON 0x01 //Test Configuration //CONFIG 0x3f COP, ROM & EEPROM enables (EEPROM cells) #define NOSEC 0x08 //Security Mode (=0 enable, 1= disable) #define NOCOP 0x04 //COP System ON (=0 enable, 1= disable) #define ROMON 0x02 //No-ROM Mode Select bit #define EPON 0x02 //EEPOM on (alternative name) // //. 0= disable ROM & use external memory // //. 1= enable ROM #define EEON 0x01 //No-EEPROM Mode Select bit // //. 0= disable 512 byte EEPROM & use external memory // //. 1= enable EEPROM //end