//super8f.h
//registerfields in the super8
//19940812/wjvg

//bank 0

//0x0d5 flags, system flags register
#define FLAGS_BA  (1<<0)  //bank address
#define FLAGS_FIS (1<<1)  //fast interrupt status
#define FLAGS_HCF (1<<2)  //half-carry flag
#define FLAGS_DA  (1<<3)  //decimal adjust
#define FLAGS_OF  (1<<4)  //overflow flag
#define FLAGS_SF  (1<<5)  //sign flag
#define FLAGS_ZF  (1<<6)  //zero flag
#define FLAGS_CF  (1<<7)  //carry flag

//0x0dc irq, interrupt request (read only)
#define IRQ_L0    (1<<0)  //level 0
#define IRQ_L1    (1<<1)  //level 1
#define IRQ_L2    (1<<2)  //level 2
#define IRQ_L3    (1<<3)  //level 3
#define IRQ_L4    (1<<4)  //level 4
#define IRQ_L5    (1<<5)  //level 5
#define IRQ_L6    (1<<6)  //level 6
#define IRQ_L7    (1<<7)  //level 7

//0x0dd imr, interrupt mask
#define IMR_L0    (1<<0)  //level 0
#define IMR_L1    (1<<1)  //level 1
#define IMR_L2    (1<<2)  //level 2
#define IMR_L3    (1<<3)  //level 3
#define IMR_L4    (1<<4)  //level 4
#define IMR_L5    (1<<5)  //level 5
#define IMR_L6    (1<<6)  //level 6
#define IMR_L7    (1<<7)  //level 7
#define IMR_P23      IMR_L0
#define IMR_P33      IMR_L0
#define IMR_P31      IMR_L1
#define IMR_P21      IMR_L1
#define IMR_UART_TD  IMR_L1
#define IMR_UART_ZC  IMR_L1
#define IMR_C0_ZC    IMR_L2
#define IMR_P26      IMR_L2
#define IMR_P27      IMR_L2
#define IMR_P22      IMR_L3
#define IMR_P32      IMR_L3
#define IMR_P24      IMR_L4
#define IMR_P25      IMR_L4
#define IMR_C1_ZC    IMR_L5
#define IMR_P36      IMR_L5
#define IMR_P37      IMR_L5
#define IMR_P20      IMR_L6
#define IMR_UART_RD  IMR_L6
#define IMR_P30      IMR_L6
#define IMR_UART_BRK IMR_L6
#define IMR_UART_CC  IMR_L6
#define IMR_UART_WU  IMR_L6
#define IMR_UART_ERR IMR_L6
#define IMR_P34      IMR_L7
#define IMR_P35      IMR_L7

//0x0de sym, system mode
#define SYM_GIE   (1<<0)  //global interrupt enable
#define SYM_FIE   (1<<1)  //fast interrupt enable
#define SYM_FIL0  (0<<2)  //fast interrupt level 0
#define SYM_FIL1  (1<<2)  //fast interrupt level 1
#define SYM_FIL2  (2<<2)  //fast interrupt level 2
#define SYM_FIL3  (3<<2)  //fast interrupt level 3
#define SYM_FIL4  (4<<2)  //fast interrupt level 4
#define SYM_FIL5  (5<<2)  //fast interrupt level 5
#define SYM_FIL6  (6<<2)  //fast interrupt level 6
#define SYM_FIL7  (7<<2)  //fast interrupt level 7
#define SYM_M_FIL (7<<2)  //fast interrupt level, masker

//0x0e0 c0ct, counter 0 control
//0x0e1 c1ct, counter 1 control
#define CCT_EC    (1<<0)  //enable counter
#define CCT_EOC   (1<<1)  //end of count
#define CCT_ZCIE  (1<<2)  //zero count interrupt enable
#define CCT_SC    (1<<3)  //software capture
#define CCT_ST    (1<<4)  //software trigger
#define CCT_LC    (1<<5)  //load counter
#define CCT_CU    (1<<6)  //count up
#define CCT_C     (1<<7)  //continuous/single cycle

//0x0eb utc, UART transmit control
#define UTC_TDE   (1<<0)  //transmit DMA enable
#define UTC_TBE   (1<<1)  //transmit buffer empty
#define UTC_ZC    (1<<2)  //zero count
#define UTC_TE    (1<<3)  //transmit enable
#define UTC_WUE   (1<<4)  //wake-up enable
#define UTC_2SB   (1<<5)  //2/1 stop bits
#define UTC_SB    (1<<6)  //send break
#define UTC_TDS   (1<<7)  //transmit data select: UART/p31

//0x0ec urc, UART receive control
#define UTC_RCA   (1<<0)  //receive character available
#define UTC_RE    (1<<1)  //receive enable
#define UTC_PE    (1<<2)  //parity error
#define UTC_OE    (1<<3)  //overrun error
#define UTC_FE    (1<<4)  //framing error
#define UTC_BD    (1<<5)  //break detect
#define UTC_CCD   (1<<6)  //control character detect
#define UTC_WUD   (1<<7)  //wake-up detect

//0x0ed uie, UART interrupt enable
#define UTC_RCAIE (1<<0)  //receive character available interrupt enable
#define UTC_RDE   (1<<1)  //receive DMA enable
#define UTC_TIE   (1<<2)  //transmit interrupt enable
#define UTC_ZCIE  (1<<3)  //zero count interrupt enable
#define UTC_REIE  (1<<4)  //receive error interrupt enable
#define UTC_BIE   (1<<5)  //break interrupt enable
#define UTC_CCIE  (1<<6)  //control character interrupt enable
#define UTC_WUIE  (1<<7)  //wake-up interrupt enable

//0x0f1 pm, port mode (write only)
#define PM_P0I    (1<<0)  //port 0 input
#define PM_P0OD   (1<<1)  //port 0 open-drain
#define PM_P1OD   (1<<2)  //port 1 open-drain
#define PM_EDM    (1<<3)  //enable DM p35
#define PM_P1I    (1<<4)  //port1 input (overruled by next bit)
#define PM_P1AD   (1<<5)  //port1 address/data (overrules previous bit)

//0x0f4 h0c, handshake 0 control (write only)
//0x0f5 h1c, handshake 1 control (write only)
#define HC_HE     (1<<0)  //handshake enable
#define HC_PS1    (1<<1)  //port select 1/4 (only for h0c)
#define HC_DE     (1<<2)  //DMA enable (only for h0c)
#define HC_FIM    (1<<3)  //fully interlocked/strobed mode
#define HC_F_DC   (1<<4)  //deskew counter (1..16) factor

//port modes
#define PM_I          0  //input
#define PM_IIE        1  //input, interrupt enabled
#define PM_OPP        2  //output, push-pull
#define PM_OOD        3  //output, open-drain
#define PM_M          3  //mask

//0x0f8 p2am, port 2/3 a mode (write only)
#define P2AM_F_P20  (1<<0)  //port 20, faktor
#define P2AM_F_P21  (1<<2)  //port 21, faktor
#define P2AM_F_P30  (1<<4)  //port 30, faktor
#define P2AM_F_P31  (1<<6)  //port 31, faktor
#define P2AM_M_P20  (3<<0)  //port 20, masker
#define P2AM_M_P21  (3<<2)  //port 21, masker
#define P2AM_M_P30  (3<<4)  //port 30, masker
#define P2AM_M_P31  (3<<6)  //port 31, masker

//0x0f9 p2bm, port 2/3 b mode (write only)
#define P2BM_F_P22  (1<<0)  //port 22, faktor
#define P2BM_F_P23  (1<<2)  //port 23, faktor
#define P2BM_F_P32  (1<<4)  //port 32, faktor
#define P2BM_F_P33  (1<<6)  //port 33, faktor
#define P2BM_M_P22  (3<<0)  //port 22, masker
#define P2BM_M_P23  (3<<2)  //port 23, masker
#define P2BM_M_P32  (3<<4)  //port 32, masker
#define P2BM_M_P33  (3<<6)  //port 33, masker

//0x0fa p2cm, port 2/3 c mode (write only)
#define P2CM_F_P24  (1<<0)  //port 24, faktor
#define P2CM_F_P25  (1<<2)  //port 25, faktor
#define P2CM_F_P34  (1<<4)  //port 34, faktor
#define P2CM_F_P35  (1<<6)  //port 35, faktor
#define P2CM_M_P24  (3<<0)  //port 24, masker
#define P2CM_M_P25  (3<<2)  //port 25, masker
#define P2CM_M_P34  (3<<4)  //port 34, masker
#define P2CM_M_P35  (3<<6)  //port 35, masker

//0x0fb p2dm, port 2/3 d mode (write only)
#define P2DM_F_P26  (1<<0)  //port 26, faktor
#define P2DM_F_P27  (1<<2)  //port 27, faktor
#define P2DM_F_P36  (1<<4)  //port 36, faktor
#define P2DM_F_P37  (1<<6)  //port 37, faktor
#define P2DM_M_P26  (3<<0)  //port 26, masker
#define P2DM_M_P27  (3<<2)  //port 27, masker
#define P2DM_M_P36  (3<<4)  //port 36, masker
#define P2DM_M_P37  (3<<6)  //port 37, masker

//0x0ff ipr, interrupt priority register
#define IPR_01    (1<<0)  //   group a: irq0<irq1
#define IPR_243   (1<<2)  //   group b: irq2<irq34
#define IPR_34    (1<<3)  //subgroup b: irq3<irq4
#define IPR_576   (1<<5)  //   group c: irq5<irq67
#define IPR_67    (1<<6)  //subgroup c: irq6<irq7
#define IPR_ACB   (0x02)  //group priority: a<c<b
#define IPR_CBA   (0x10)  //group priority: c<b<a
#define IPR_CAB   (0x12)  //group priority: c<a<b
#define IPR_BAC   (0x80)  //group priority: b<a<c
#define IPR_ABC   (0x82)  //group priority: a<b<c
#define IPR_BCA   (0x90)  //group priority: b<c<a

//0x0fc p2aip, port 2/3 a interrupt pending (read only)
#define P2AIP_P20 (1<<0)  //port 20
#define P2AIP_P21 (1<<1)  //port 21
#define P2AIP_P30 (1<<2)  //port 30
#define P2AIP_P31 (1<<3)  //port 31
#define P2AIP_P22 (1<<4)  //port 22
#define P2AIP_P23 (1<<5)  //port 23
#define P2AIP_P32 (1<<6)  //port 32
#define P2AIP_P33 (1<<7)  //port 33

//0x0fd p2bip, port 2/3 b interrupt pending (read only)
#define P2BIP_P24 (1<<0)  //port 24
#define P2BIP_P25 (1<<1)  //port 25
#define P2BIP_P34 (1<<2)  //port 34
#define P2BIP_P35 (1<<3)  //port 35
#define P2BIP_P26 (1<<4)  //port 26
#define P2BIP_P27 (1<<5)  //port 27
#define P2BIP_P36 (1<<6)  //port 36
#define P2BIP_P37 (1<<7)  //port 37

//0x0fe emt, external memory timing register
#define EMT_DSDM   (1<<0)  //dma select: data memory/register file
#define EMT_SSDM   (1<<0)  //stack select: data memory/register file
#define EMT_F_DMAW (1<<2)  //data memory automatic waits factor
#define EMT_DMAW0  (0<<2)  //data memory automatic waits: 0
#define EMT_DMAW1  (1<<2)  //data memory automatic waits: 1
#define EMT_DMAW2  (2<<2)  //data memory automatic waits: 2
#define EMT_DMAW3  (3<<2)  //data memory automatic waits: 3
#define EMT_F_PMAW (1<<4)  //program memory automatic waits factor
#define EMT_PMAW0  (0<<4)  //program memory automatic waits: 0
#define EMT_PMAW1  (1<<4)  //program memory automatic waits: 1
#define EMT_PMAW2  (2<<4)  //program memory automatic waits: 2
#define EMT_PMAW3  (3<<4)  //program memory automatic waits: 3
#define EMT_SMTE   (1<<6)  //slow memory timing enable
#define EMT_P34EWI (1<<7)  //p34: external wait input/normal i/o

//bank 1

//0x1e0 c0m, counter 0 mode
//0x1e1 c1m, counter 1 mode
#define CM_NC             (0<<0)  //no capture
#define CM_CORE           (1<<0)  //capture on rising edge of p27
#define CM_BVM            (2<<0)  //bi-value mode
#define CM_COBE           (3<<0)  //capture on both edges of p27
#define CM_PUDC           (1<<2)  //programmed/external up/down control (p27)
#define CM_ER             (1<<3)  //enable retrigger
//                                //p26          p27
#define CM_P26_IO__P27_IO  0x00   //i/o          i/o
#define CM_P26_T___P27_IO  0x10   //trigger      i/o
#define CM_P26_IO__P27_G   0x20   //i/o          gate
#define CM_P26_T___P27_G   0x30   //triggger     gate
#define CM_P26_C0I_P27_IO  0x40   //c0input      i/o
#define CM_P26_C0I_P27_T   0x50   //c0input      trigger
#define CM_P26_C0I_P27_G   0x60   //c0input      gate
#define CM_P26_C0I_P27_GT  0x70   //c0input      gate/trigger
#define CM_P26_IO__P27_C0O 0x80   //i/o          c0output
#define CM_P26_T___P27_C0O 0x90   //trigger      c0output
#define CM_P26_G___P27_C0O 0xa0   //gate         c0output
#define CM_P26_GT__P27_C0O 0xb0   //gate/trigger c0output
#define CM_P26_C0I_P27_C0O 0xb0   //c0input      c0output
#define CM_CC              0xf0   //cascade counters (alleen in c0m)

//0x1fa uma, UART mode a
#define UMA_TWUV  (1<<0)  //transmit wake-up value
#define UMA_TWUV  (1<<1)  //receive wake-up value
#define UMA_TWUV  (1<<2)  //even parity
#define UMA_TWUV  (1<<3)  //parity enable
#define UMA_F_B   (1<<4)  //bits factor (number of bits-5)
#define UMA_5B    (0<<4)  //5 bits
#define UMA_6B    (1<<4)  //6 bits
#define UMA_7B    (2<<4)  //7 bits
#define UMA_8B    (3<<4)  //8 bits
#define UMA_F_X   (1<<6)  //clock rate factor
#define UMA_X1    (0<<6)  //clock rate x1
#define UMA_X16   (1<<6)  //clock rate x16
#define UMA_X32   (2<<6)  //clock rate x32
#define UMA_X64   (3<<6)  //clock rate x64

//0x1fb umb, UART mode b
#define UMB_LE    (1<<0)  //loopback enable
#define UMB_BRGE  (1<<1)  //baud-rate generator enable
#define UMB_BRGSI (1<<2)  //baud-rate generator source: internal/external
#define UMB_TCIB  (1<<3)  //transmit clock input select: brg/p21
#define UMB_RCIB  (1<<4)  //receive clock input select: brg/p20
#define UMB_AE    (1<<5)  //auto echo
#define UMB_COP21 (0<<6)  //clock output select: p21 data
#define UMB_COSC  (1<<6)  //clock output select: system clock (xtal/2)
#define UMB_COBRG (2<<6)  //clock output select: baud-rate generator output
#define UMB_COTDC (3<<6)  //clock output select: transmit data clock

//end